Vladimir State University,
600000, Russia, Vladimir, Gorky-Street, 87
Nowadays systems for optical quality control of details of surfaces
are a part of the system for quality control of manufactured wares in many
plants. Such systems provide a plant with ample opportunity to control the
quality of surfaces of every detail and they are necessary for the production
of a plant to correspond with the international standard ISO 9000. Systems
for optical quality control (SOQC) consist of 3 main components:
1. devices which are used in order to receive visual information about the
surfaces (video cameras and other equipment - e.g. endoscopes, light
2. devices of information processing (primarily image processing);
3. devices for visualizing the processed results (CRT and LCD monitors,
displays, etc.).
Today, SOQC are often built on the base of PCs (personal com-
puters). Video cameras and other equipment are connected through a frame
grabber or through a standard interface (e.g., USB or FireWire). In this case
the PC is both the system of information processing and the device for visu-
alizing the results. The most important disadvantages of such SOQC are
- high price (more than 50,000 euros);
- low performance (as a result of the software implementation of the algo-
- low reliability (due to the complexity of the system).
At first these disadvantages are defined by the PC because it is a
multifunctional, general-purpose and non-specialized system. Such com-
puters are very convenient for simulating the algorithms of image process-
ing and for use in solitary systems, but they are not suitable for the efficient
execution of special functions.
The main goal of the SOQC is to remove human subjectivity from
the process of the defects inspection. However, it is very difficult to do be-
cause the price of such systems is very high. Hence, the best solution for
SOQC is the implementation of the image processing algorithms on the
base of the adaptive computing system (ACS) which consists of a dynamic
reconfigurable field programmable gate array (FPGA), a processor, and
configuration memory. This obstacle decreases the price of the system (be-
cause the PC hardware is redundant for image processing tasks) while si-
multaneously increasing the performance of the system (e.g. by means of
parallel calculations and the efficient execution of special functions). For
the implementation of this ACS, the state-of-the-art architectures have been

developed. The structure of the designed ACS is shown in fig. 1. The com-
ponents which have been used for the implementation of the ACS are de-
scribed in table 1.
1 button
8 buttons
8 LEDs
1 digit numeric
+2.5V +3.3V +5V
8symb 2lines

Fig.1. The structure of the designed ACS
Nowadays, there are a lot of algorithms which are used for the auto-
mated inspection of defects on the surfaces of details and whose foundation
is "human-like" image segmentation. Adaptive thresholding methods form
the basis of the majority of the algorithms. To implement these algorithms,
we have to calculate a lot of different functions (both elementary and
compound ones). It is necessary, for instance, to compute the evolvent of
cylindrical and other surfaces. If these image processing algorithms are
implemented on the base of FPGAs, then it is possible to avoid additional
operations (command decoding in a processor, data exchange between
arithmetic and general-purpose registers, etc). Besides this benefit,
specialized FPGA configurations can be designed for the execution of
different compound operations. Such an approach provides the possibility to
calculate compound functions in the same amount of time as elementary
ones (e.g. sinx, cosx, tanx, square root).
Another important advantage of the suggested approach is that the
microcontroller and the FPGA, which are integrated in the special-purpose
computer, can execute parallel calculations. For the realization of the paral-
lel calculations, it is expedient to use the model of a multiprocessor system
with shared memory. This means that the special-purpose computer has a
common data memory through which the microcontroller and the FPGA
exchange data. This approach is a very efficient and easy way to implement
parallel computing and to reduce the calculation time. In addition, the mi-

crocontroller and the FPGA are able to have subsidiary memory blocks for
temporary data which helps to avoid frequent references to the shared

Table 1 - The description of components on the circuit board
Component or parameter Description
FPGA EP1K100QC208-3
Microcontroller ATMEGA8L-8PI
Static RAM (SRAM)
AS7C34096 (8512 Kbits)
Reprogrammable Flash
AT45DB081B (8 Mbits)
configuration memory
Input means
LPT-port (EPP), 42 pins and 9 buttons
Output means
LPT-port (EPP), 42 pins, LCD (2 lines by 8
symbols), 1 digit numeric display, 8 LEDs
Data exchange between the 10 bits bus
microcontroller and the
Working voltage
(AC/DC) 9-15 V

A prototype of such a system was designed and implemented using a
software and hardware complex (fig. 2). The software was used solely for
the verification of the hardware implementation. Thus, designing this com-
plex consisted of the following steps:
1. The software implementation of the adaptive thresholding algo-
2. The hardware implementation of these algorithms.
3. The verification of the hardware implementation by means of the
If the designed variant of the hardware implementation is not correct,
the second and third steps can be repeated; that is this design process be-
comes the iterative one.
The circuit board which was used for the hardware implementation
costs about 80 euros. In it the parallel and fast calculations were not imple-
mented and the cheapest hardware (e.g. microcontroller, SRAM and con-
figuration memory) was used. For the software implementation, a PC with
the following parameters was used: processor - Pentium 4, 3 GHz; dynamic
RAM - 1 Gbyte SDRAM; harddisk - 200 Gbyte; monitor - Benq TFT 17'',
operating system - Windows XP.
The results which were obtained during the research are respectively
presented in table 2 (the performances of the software and hardware imple-
mentations are shown for the averaging method). From table 2, we can see
that the ratio of the prices is 12.5, but the ratio of the performances - 3.5.

These data prove that the hardware implementation is a very efficient means
for price reduction and / or for performance increase. In order to reach the
performance of the software implementation, several modules can be used
in parallel.

Fig. 2: The structure of the designed software and hardware complex
Table 2 - The comparison of the software and hardware implementations
Type of imple- Price of the used hard- Performance in millions
ware in euros
of processing pixels per
Software im- 995.75 35
Hardware im- 79.5 10

As a way to further increase performance, the following approach is
suggested. The image processing algorithms are implemented both as soft-
ware (for a digital signal processor - DSP) and as hardware (as a configura-
tion for FPGA). Typical operations for digital signal processing algorithms
(e.g. addition with result accumulation, MAC operations) are implemented
in a DSP and non-typical (for digital signal processing) ones which are re-
peated a lot of times are implemented in a FPGA (e.g. the calculation of the
evolvent of cylindrical and other surfaces).

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